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Synopsys

Validation / Verification Eng, Manager - 18754

Ottawa, ON, Canada

Experience: 8+ years of hands-on silicon validation experience with memory interfaces such as DDR, LPDDR, or HBM
Posting language: English
Posted: Sep 10, 2026

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Original job description

General Information

Job Title

Validation / Verification Eng, Manager - 18754

Job ID

18754

Country

Canada

City

Nepean

State/Province

Nepean

Date Posted

10-Sep-2026

Job Category

Engineering

Job Subcategory

Validation / Verification Eng

Hire Type

Employee

Remote Eligible

Descriptions & Requirements

Job Description and Requirements

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years in the lab watching what happens when theory meets reality. First silicon never behaves exactly as simulated, and you have built a career on figuring out why and what to do about it.

Managing people and projects simultaneously energizes you. You have led teams through bring-up/"Power On" chaos, kept schedules on track while debugging signal integrity issues, and hired engineers who became your best validators.

You think in test plans, not checklists. When a DDR eye diagram looks wrong, you systematically isolate the problem until you find it. At Synopsys, you will lead a lab team validating memory IP that ships in products worldwide.

What You'll Be Doing
* Lead first silicon bring-up and validation for DDR6, DDR5, LPDDR6/X, LPDDR5/5X, MRDIMM, and HBM test chips
* Perform electrical characterization including eye diagrams, jitter measurements, timing margins, and signal integrity analysis
* Drive debug and root cause analysis of silicon, firmware, and board issues using lab instrumentation and cross-functional collaboration
* Build automated validation frameworks using Python and C/C++ to improve test efficiency and data collection
* Lead multilayer PCB design for characterization platforms and customer evaluation kits
* Manage team hiring, staffing, resource allocation, morale and audit preparation while growing technical capability
* Work alongside cross-functional teams including but not limited to stakeholders, marketing, sales, customers, program/foundry as well as other lab managers and teams to weigh business impacts and make critical decisions
* Manage Gate Review and Kickoff Meetings, in addition to Characterization Plan and Report publications, checklists and supporting documentation

The Impact You Will Have
* Ensure Synopsys memory interface IP products meet performance and reliability standards before customer deployment
* Implement efficiency improvements and process changes to a team of 20+ staff across 3+ labs
* Reduce time to market by building reusable test infrastructure that accelerates validation across IP generations
* Provide silicon-proven characterization data that gives customers confidence to integrate Synopsys IP
* Identify and resolve issues early, preventing costly re-spins and customer escalations
* Grow a high-performing validation team in Nepean that becomes a center of excellence for memory IP
* Influence design decisions by feeding back real-world silicon behavior to architecture teams

What You'll Need
* Bachelor's degree in Electrical Engineering or equivalent technical field
* 8+ years of hands-on silicon validation experience with memory interfaces such as DDR, LPDDR, or HBM
* 3+ years managing engineering teams, including hiring and resource allocation
* Deep understanding of JEDEC specifications, jitter analysis, timing margins, and electrical characterization
* Proficiency in Python and C for test automation and hardware validation scripting
* Experience with ATE testers such as Teradyne, LTX/Credence, Advantest
* Board design experience including multilayer PCB development, experience with automotive qualification standards or reliability testing is a plus
* Experience in scheduling, event planning with vendors of all sorts

Who You Are
* You can walk into a lab, look at a failing test result, and within an hour have a hypothesis and a plan to prove it
* You manage people with strong listening skills as well as by growing their skills, not micromanaging tasks, and your team knows you will back them and to trust you
* You can explain a complex silicon debug finding to a design lead in two sentences without losing the nuance
* You balance project deadlines and team development without sacrificing either
* You are comfortable operating oscilloscopes, BERTs, and network analyzers, and expect your team to be equally hands-on
* You are meticulously well organized and have a strong attention to detail with a capacity to juggle several priority items at once in a high-stress, fast-paced environment

The Team You'll Be Part Of

You will join the growing Nepean lab team focused on validating Synopsys' memory interface IP portfolio. This is a hands-on lab environment where you will work closely with firmware and design groups to bring new IP from silicon bring-up through production release. The team operates at the intersection of design intent and real-world silicon behavior, and your work will directly inform product readiness and customer deployments.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.

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More about this job

Responsibilities

Lead first silicon bring-up and validation for memory interface IP while managing a team of engineers across multiple labs. Drive debug and root cause analysis of silicon, firmware, and board issues to ensure product performance and reliability.

Requirements

Requires a Bachelor's degree in Electrical Engineering with over 8 years of hands-on silicon validation experience. Candidates must have at least 3 years of engineering management experience and proficiency in Python and C for test automation.

Skills

Silicon validation
DDR memory
LPDDR
HBM
Electrical characterization
Signal integrity
Python
C++
PCB design
Team management
JEDEC specifications
Jitter analysis
Timing margins
ATE testers
Root cause analysis
Hardware validation

Benefits

Health benefits
Wellness benefits
Financial benefits

Visa sponsorship

Not detected in the job text

Keywords

Silicon validation
DDR6
DDR5
LPDDR6
LPDDR5
MRDIMM
HBM
Electrical characterization
Eye diagrams
Jitter measurements
Signal integrity
Python
C++
PCB design
ATE testers
Teradyne
Advantest
JEDEC
Firmware
Silicon bring-up
Engineering management
Validation frameworks
Root cause analysis
Memory IP
Hardware validation
Oscilloscopes
BERTs
Network analyzers
Automotive qualification
Reliability testing

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