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Added 6 mins ago
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Quality Engineer I
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- Full-time
…test creation and process support, to deliver high-quality solutions through automation and enhancement of testing…
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TekWissen ®

ASIC/RTL Design Engineer 5

Vaughan, ON, Canada

$89.11 to $94.06 CAD / hour · Contract

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Job details

Pay: $89.11 to $94.06 CAD / hour
Job type: Contract
Apply by: Dec 3, 2026
Posting language: English
Posted: Nov 3, 2026

Original job description

Job Title: ASIC/RTL Design Engineer 5

Location: MARKHAM, ON L3T 7X6

Duration: 12 Months

Job Type: Temporary Assignment

Work Type: Hybrid

Pay Rate: $89.11 - $94.06/Hr

Overview:

TekWissen is a global workforce management provider headquartered in Ann Arbor, Michigan that offers strategic talent solutions to our clients world-wide. This Client is an American multinational semiconductor company based in Santa Clara, California, that develops computer processors and related technologies for business and consumer markets. Global company that specializes in manufacturing semiconductor devices used in computer processing. The company also produces flash memories, graphics processors, motherboard chip sets, and a variety of components used in consumer electronics goods.

Job Description:

THE ROLE:

In this role, you will be responsible for driving low-power design strategies, synthesis, and timing closure for complex SoC and IP designs.
You will use industry-standard EDA tools to optimize power, performance, and area (PPA), ensuring efficient, reliable silicon that meets product requirements.

THE PERSON:

You are passionate about digital design, power optimization, and timing closure in advanced semiconductor technologies.
You enjoy solving challenging problems, are detail-oriented, and thrive in a collaborative team environment and passionate to work with vibrant team located in different time zone.
With strong analytical skills and a methodical approach, you are eager to learn, share knowledge, and contribute to building cutting-edge silicon.

KEY RESPONSIBILITIES:

Develop and implement power reduction strategies across SoC/IP design.
Perform synthesis and static timing analysis (STA) to achieve PPA targets.
Analyze and optimize dynamic and leakage power using industry-standard tools.
Work closely with RTL designers, physical design, and verification teams to ensure timing and power requirements are met.
Run low-power verification checks (UPF/CPF) and validate correct power intent implementation.
Support sign-off activities for Lint, CDC, synthesis, timing, and power closure.
Automate and streamline power and timing workflows to improve efficiency.
Build test plan documentation, accounting for interactions with other features, the hardware.

PREFERRED EXPERIENCE:

Strong background in ASIC synthesis and static timing analysis (STA).
Hands-on expertise with EDA tools such as Synopsys Design Compiler, PrimeTime, PrimePower, Power Artists, or equivalent.
Experience with power analysis and optimization techniques (clock gating, multi-Vt, power gating, multi-voltage design).
Familiarity with UPF/CPF power intent specification and verification.
Solid understanding of digital design fundamentals, RTL coding (Verilog/SystemVerilog).
Experience with advanced process nodes (e.g., 7nm, 5nm, 3nm) is a strong plus.
Proficiency in scripting languages (TCL, Perl, Python, or Shell) for flow automation.
Exposure to floorplanning, place-and-route, and ECO flows is desirable.
Knowledge of low-power design methodologies and trade-offs.
Prior leadership, mentorship, or cross-functional collaboration experience is an asset.
Experienced with Verilog, System Verilog, C, and C++.
Graphics pipeline knowledge.
Automating workflows in a distributed compute environment.

TekWissen® Group is an equal opportunity employer supporting workforce diversity.

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More about this job

Responsibilities

Develop and implement low-power strategies for SoC and IP designs, performing synthesis, static timing analysis, and power optimization to meet power, performance, and area targets. Collaborate with RTL, physical design, and verification teams on power intent, sign-off, workflow automation, and test-plan documentation.

Requirements

The role calls for strong ASIC synthesis and static timing analysis experience, knowledge of digital design and RTL coding, and hands-on familiarity with industry-standard EDA tools and low-power methods. Scripting skills and experience with advanced process nodes, physical design flows, graphics pipelines, or cross-functional leadership are advantageous.

Skills

ASIC Synthesis
Static Timing Analysis
Low-Power Design
Power Optimization
Power, Performance, And Area Optimization
Verilog
SystemVerilog
UPF/CPF
Synopsys Design Compiler
PrimeTime
PrimePower
Power Artists
TCL
Perl
Python
Shell Scripting

Visa sponsorship

Not detected in the job text

Keywords

ASIC
RTL
SoC
IP Design
Synthesis
Static Timing Analysis
Power Optimization
Low-Power Design
Power, Performance, And Area
Dynamic Power
Leakage Power
Clock Gating
Multi-Vt
Power Gating
Multi-Voltage Design
UPF
CPF
Verilog
SystemVerilog
C
C++
Synopsys Design Compiler
PrimeTime
PrimePower
Power Artists
TCL
Perl
Python
Shell Scripting
Lint

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