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Teledyne Technologies Incorporated

Analog IC Layout Designer

Waterloo, ON, Canada
Canada - Waterloo, ON, Canada

$93,700.00-$124,900.000 · Full-time

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Job details

Pay: $93,700.00-$124,900.000
Job type: Full-time
Experience: Required: 3+ years of analog/mixed-signal IC layout experience.
Posting language: English
Posted: Oct 30, 2026

Original job description

Be visionary

Teledyne Technologies Incorporated provides enabling technologies for industrial growth markets that require advanced technology and high reliability. These markets include aerospace and defense, factory automation, air and water quality environmental monitoring, electronics design and development, oceanographic research, deepwater oil and gas exploration and production, medical imaging and pharmaceutical research.

We are looking for individuals who thrive on making an impact and want the excitement of being on a team that wins.

Job Description

Join a team developing high-performance analog and mixed-signal ICs for CMOS image sensor applications. You’ll turn transistor-level designs into robust silicon layouts, balancing matching, noise, area, reliability, and manufacturability.

If you enjoy solving layout-dependent performance challenges and collaborating closely with analog designers from schematic through tapeout, this role offers meaningful technical depth within Teledyne Technologies.

What you’ll do

Create transistor- and block-level layouts for Op-Amps, references, ADC/DACs, PLLs, sensor readout, and high-speed interfaces.
Optimize floorplans for matching, area, noise isolation, power integrity, and EM reliability.
Apply common-centroid, interdigitation, symmetry, shielding, guard-ring, and dummy-device techniques.
Run and resolve DRC, LVS, ERC, density, and fill verification.
Minimize parasitic coupling, process variation, and layout-dependent effects.
Support parasitic extraction, post-layout simulation, and tapeout.
Collaborate with design, process, reliability, verification, and CAD teams.
Contribute to layout reviews and mentor junior engineers when appropriate.

What you need

Required: Strong understanding of analog matching, parasitics, device physics, ESD, and reliability.
Required: Ability to interpret transistor-level schematics and analog circuit behavior.
Required: 3+ years of analog/mixed-signal IC layout experience.
Required: Experience with advanced CMOS technologies and signoff.
Required: Proficiency with Cadence Virtuoso and Calibre, Assura, or equivalent tools.
Required: Bachelor’s or Master’s degree in EE, Computer Engineering, Physics, or related field.
Advantage: CIS, ADC/DAC, PLL, high-voltage, or low-noise sensor-interface experience.
Advantage: EM/IR, LDE, ESD/latch-up, advanced-node, and tapeout experience.

What we offer

Technically challenging work on advanced sensor ICs.
Collaboration across deep engineering disciplines.
Opportunities to expand analog layout and silicon expertise.
Exposure to designs from block level through integration and tapeout.
The stability and engineering breadth of Teledyne Technologies.

What happens next

Applications are reviewed first, followed by a recruiter screen and technical/team interviews for selected candidates. Timelines vary by role and candidate availability.

Teledyne Technologies is an equal opportunity employer.

Salary Range:

$93,700.00-$124,900.000

The anticipated salary range listed for this role is only an estimate. Actual compensation for successful candidates is carefully determined based on several factors including, but not limited to, location, local regulations (such as minimum wage), education/training, work experience, key skills, and type of position.

Teledyne and all of our employees are committed to conducting business with the highest ethical standards. We require all employees to comply with all applicable laws, regulations, rules and regulatory orders. Our reputation for honesty, integrity and high ethics is as important to us as our reputation for making innovative sensing solutions.

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More about this job

Responsibilities

Create transistor- and block-level layouts for high-performance analog and mixed-signal ICs while optimizing for matching, noise, and reliability. Collaborate with design, process, and CAD teams to resolve verification issues and support the full tapeout process.

Requirements

Requires at least 3 years of analog/mixed-signal IC layout experience and proficiency with Cadence Virtuoso and verification tools. Candidates must hold a Bachelor's or Master's degree in a relevant engineering or physics field.

Skills

Analog IC Layout
Mixed-signal IC
CMOS
Cadence Virtuoso
Calibre
Assura
Transistor-level design
Floorplanning
DRC
LVS
ERC
Parasitic extraction
Tapeout
ESD
Device physics
Op-Amps

Visa sponsorship

Not detected in the job text

Keywords

Analog IC Layout
Mixed-signal
CMOS
Cadence Virtuoso
Calibre
Assura
DRC
LVS
ERC
Tapeout
Op-Amps
ADC
DAC
PLL
Parasitic extraction
ESD
Device physics
Floorplanning
Common-centroid
Interdigitation
Shielding
Guard-ring
Dummy-device
EM reliability
Power integrity
Sensor readout
High-speed interfaces
Layout-dependent effects
Post-layout simulation
Advanced-node

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