Design Verification Engineer
- Vancouver, BC, Canada
Contract
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Job details
- Job type
- Contract
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- Posting language
- English
- Posted
Original job description
Job Summary
We are seeking a Design Verification Engineer to join our team. You will
work with architects, designers, and vendors to ensure that all our architecture
requirements are met in the IP subsystems and interfaces being created, validate
correctness and performance across the full hardware-software stack. This role
demands creativity, deep technical ability, and the drive to tackle complex verification
challenges.
Key responsibilities
- End to end ownership of one or more of the following IP subsystems: PCIe,
Ethernet, CPU (arc/arm), low power peripherals, sensors
- Understand vendor IP configurations and handle handshake with internal IP team
- Develop and maintain UVM/SystemVerilog-based verification environments to
ensure functional correctness, performance, and compliance with IP
specifications.
- Collaborate with integration and SoC DV teams to validate seamless interaction
of external IPs within the broader chip architecture.
- Drive coverage closure and sign-off by defining metrics, analyzing gaps, and
ensuring comprehensive verification across corner cases and stress scenarios
More about this job
Responsibilities
Own verification for one or more IP subsystems, coordinate vendor IP configuration with internal teams, and develop UVM/SystemVerilog environments to verify functionality, performance, and specification compliance. Collaborate with integration and SoC verification teams, and drive coverage analysis and sign-off across corner cases and stress scenarios.
Requirements
The role calls for deep technical ability and experience with hardware design verification, UVM/SystemVerilog, and IP subsystems. It also requires collaboration with architects, designers, vendors, and SoC teams to validate IP integration and close verification coverage.
Skills
- Design Verification
- UVM
- SystemVerilog
- Functional Verification
- Performance Verification
- IP Subsystems
- PCIe
- Ethernet
- CPU Architecture
- Low-Power Peripherals
- Sensors
- Vendor IP Configuration
- SoC Integration
- Coverage Closure
- Verification Sign-Off
- Hardware-Software Validation
Visa sponsorship
Not detected in the job text
Categories
- Engineering
- Technology
- Software
Keywords
- Design Verification
- UVM
- SystemVerilog
- IP Subsystems
- PCIe
- Ethernet
- CPU
- ARC
- ARM
- Low-Power Peripherals
- Sensors
- Vendor IP
- IP Configuration
- Handshake
- Functional Correctness
- Performance Verification
- IP Specifications
- SoC
- Integration
- Coverage Closure
- Verification Metrics
- Coverage Analysis
- Corner Cases
- Stress Scenarios
- Hardware-Software Stack