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Design Verification Engineer
- Vancouver, BC, Canada
Contract
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- Job type
- Contract
- Closing date
- Posting language
- English
- Posted
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Job Title: Design Verification Engineer
Location: Vancouver, BC, Canada - Initial 1 month Hybrid then after Remote
Job Summary
We are looking for a Design Verification Engineer with strong experience in ASIC/SoC verification to develop and execute verification environments and ensure high-quality digital designs.
Responsibilities
- Develop verification environments and testbenches using SystemVerilog and UVM.
- Create and execute functional, regression, and constrained-random tests.
- Analyze functional/code coverage and drive coverage closure.
- Debug RTL and simulation failures and work with design teams to resolve issues.
- Verify protocols such as AMBA/AXI, PCIe, Ethernet, or similar interfaces.
- Automate testing and regression using Python, Perl, or Shell scripting.
Required Skills
- Strong SystemVerilog & UVM experience.
- Solid understanding of RTL, digital design, and ASIC/SoC verification.
- Experience with simulation tools such as VCS, Xcelium, or Questa.
- Strong debugging and scripting skills.
- Bachelor's/Master's degree in Electrical, Electronics, or Computer Engineering.
More about this job
Responsibilities
Develop SystemVerilog and UVM verification environments and testbenches, and create and run functional, regression, and constrained-random tests. Analyze coverage, debug RTL and simulation failures, verify interface protocols, and automate testing and regressions.
Requirements
Requires strong SystemVerilog and UVM experience, solid knowledge of RTL, digital design, and ASIC/SoC verification, and experience with VCS, Xcelium, or Questa. Also requires strong debugging and scripting skills and a bachelor's or master's degree in Electrical, Electronics, or Computer Engineering.
Skills
- SystemVerilog
- UVM
- ASIC/SoC Verification
- RTL
- Digital Design
- Functional Verification
- Constrained-Random Testing
- Regression Testing
- Functional Coverage
- Code Coverage
- Debugging
- AMBA/AXI
- PCIe
- Ethernet
- Python
- Perl
Visa sponsorship
Not detected in the job text
Categories
- Engineering
- Technology
- Software
Keywords
- ASIC
- SoC
- Design Verification
- SystemVerilog
- UVM
- RTL
- Digital Design
- Testbenches
- Functional Testing
- Regression Testing
- Constrained-Random Testing
- Functional Coverage
- Code Coverage
- Coverage Closure
- VCS
- Xcelium
- Questa
- AMBA
- AXI
- PCIe
- Ethernet
- Python
- Perl
- Shell Scripting
- Simulation
- Electrical Engineering
- Electronics Engineering
- Computer Engineering