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US Tech Solutions

RTL Verification Engineer # 26-23383

Markham, ON, Canada

$80 to $100 USD / hour · Contract

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Job details

Pay: $80 to $100 USD / hour
Job type: Contract
Apply by: Nov 25, 2026
Posting language: English
Posted: Oct 26, 2026

Original job description

Duration: 8 months
Description:
As a Verification Engineer 5, you will play a key role in defining, developing, and executing advanced verification solutions for complex Display IP and SoC designs.
You will work closely with architects, design engineers, software teams, and program managers to ensure first-pass silicon success and deliver high-quality products to market.
The ideal candidate is passionate about verification methodologies, possesses strong expertise in System Verilog/UVM-based verification environments, and has hands-on experience with formal verification, functional coverage planning, and coverage-driven verification. This individual will thrive in a collaborative environment and enjoy solving complex technical challenges across all phases of product development.
Key Responsibilities

Define and execute comprehensive verification strategies for complex IP and subsystem designs.
Develop verification plans based on architecture and design specifications.
Design, implement, and maintain scalable SystemVerilog/UVM testbenches and reusable verification components.
Create directed and constrained-random test scenarios to validate functionality, performance, and robustness.
Develop functional coverage plans and coverage models, and drive coverage closure.
Define verification signoff criteria using simulation, functional coverage, assertion coverage, and formal verification metrics.
Apply formal verification methodologies including property checking, assertion development, protocol verification, and design correctness analysis.
Develop and maintain assertion-based verification (SVA) infrastructure and verification content.
Perform debugging and root-cause analysis of simulation, formal verification, and silicon issues.
Collaborate closely with architects, RTL designers, firmware, software, and validation teams throughout the product lifecycle.
Analyze verification metrics and recommend improvements to verification quality and efficiency.
Contribute to verification methodology development, automation, and continuous process improvement.

Preferred Experience

8-10 years of experience in ASIC, IP, or SoC verification.
Strong expertise in SystemVerilog, UVM, and constrained-random verification methodologies.
Proven experience developing verification plans, functional coverage models, coverage-driven verification strategies, and coverage closure.
Hands-on experience with formal verification methodologies and industry-standard formal verification tools.
Strong understanding of assertion-based verification (SVA) and formal property development.
Experience creating reusable verification environments, verification IP, and verification infrastructure.
Solid understanding of digital design concepts, computer architecture, and hardware verification methodologies.
Experience with simulation, regression management, coverage analysis, and debug tools.
Experience working through multiple successful silicon product cycles.
Strong communication and collaboration skills.

Preferred Technical Skills
Experience in one or more of the following areas is considered an asset:

Display IP and display subsystem verification
Formal verification and assertion-based verification (ABV)
Functional coverage architecture and coverage closure methodologies
Graphics, multimedia, and video processing pipelines
Display interfaces and protocols including DisplayPort, eDP, HDMI, and MIPI
High-speed interfaces and protocols
Memory subsystem verification

Academic Credentials

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.
Master's degree preferred.

What You'll Bring

Strong problem-solving and analytical skills.
Ability to work independently and drive technical initiatives.
Excellent verbal and written communication skills.
Experience leading verification efforts from planning through signoff.
Commitment to engineering excellence and product quality.
Passion to learn and adopt emerging technologies, including AI-assisted engineering tools, to enhance development efficiency and innovation.

About US Tech Solutions:
US Tech Solutions is a global staff augmentation firm providing a wide range of talent on-demand and total workforce solutions. To know more about US Tech Solutions, please visit www.ustechsolutions.com.
US Tech Solutions is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, colour, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.
AI Statement: By applying, you acknowledge that AI-assisted tools may be used during hiring.

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More about this job

Responsibilities

Define and execute verification strategies for complex IP, subsystem, and SoC designs, including developing reusable SystemVerilog/UVM testbenches, test scenarios, coverage models, assertions, and formal verification content. Debug verification issues, drive coverage and signoff, analyze verification metrics, and collaborate with architecture, design, firmware, software, and validation teams throughout product development.

Requirements

The role seeks 8–10 years of ASIC, IP, or SoC verification experience, with strong SystemVerilog, UVM, constrained-random verification, functional coverage, and formal verification expertise. A bachelor's degree in electrical engineering, computer engineering, computer science, or a related discipline is required or expected, with a master's degree preferred; experience with display technologies and protocols is an asset.

Skills

SystemVerilog
UVM
Constrained-Random Verification
Formal Verification
Functional Coverage
Coverage Closure
Assertion-Based Verification
SystemVerilog Assertions
Verification Planning
Testbench Development
Simulation and Regression Management
Debugging and Root-Cause Analysis
Display IP Verification
SoC Verification
Digital Design
Computer Architecture

Visa sponsorship

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Keywords

ASIC Verification
IP Verification
SoC Verification
Display IP
SystemVerilog
UVM
Constrained-Random Verification
Formal Verification
Functional Coverage
Coverage-Driven Verification
Coverage Closure
Assertion-Based Verification
SystemVerilog Assertions
Property Checking
Protocol Verification
Verification Planning
Reusable Verification Components
Testbench Development
Simulation
Regression Management
Coverage Analysis
Root-Cause Analysis
DisplayPort
Embedded DisplayPort
HDMI
MIPI
Graphics Processing
Video Processing
Memory Subsystem Verification
AI-Assisted Engineering Tools

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