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Added 15 hours ago
Design Engineer
ePIC ASIC
Toronto, ON
Full-time
Company Description ePIC ASIC is a semiconductor engineering company that delivers end-to-end silicon design services for advanced compute platforms, custom ASICs, and high-performance…
Added 1 day ago
Systems Validation Engineer – Data Center GPU
AMD
Markham, ON
$120,800 to $181,200 USD / year
Full-time
As a Systems Validation Engineer within the Datacenter and GPU Accelerated Processing division, you will drive SOC and system/rack level validation, triage and debug for the AMD Data Center…
Added 1 day ago
Physical Design Engineer
Qualcomm
Markham, ON
Full-time
…computing, AI, mobile, automotive, data center, and next-generation semiconductor technologies. Engineers in this role may work on different aspects of Physical Design ASIC and SoC…
Added 1 day ago
SoC RTL Design Engineer
Quadric
Canada
Full-time
Quadric is building a revolutionary new processor-based SoC architecture. As a Staff SoC RTL Engineer, you will get in on the ground floor as a key member of our chip design team,…
Added 1 day ago
SoC RTL Design Engineer
quadric, Inc
Remote, Canada
Remote
Quadric is building a revolutionary new processor-based SoC architecture. As a Staff SoC RTL Engineer, you will get in on the ground floor as a key member of our chip design team,…
Added 3 days ago
Principal Firmware Engineer
Synopsys Inc
Ottawa, ON · Nepean, ON
Full-time
Dropping into RTL waveforms to debug firmware comes naturally to you. So does stepping back to question whether the algorithm itself needs rethinking. Profiling compiled code to find…
Added 3 days ago
Principal Digital Verification Engineer
Synopsys Inc
Ottawa, ON · Nepean, ON
Full-time
…protocol details and when to just push forward on debug with RTL and firmware engineers in other time…
Added 4 days ago
Lead Validation Engineer - Data Center GPU
Advanced Micro Devices, Inc
Markham, ON
Full-time
As an Lead Domain Validation Engineer in the Data Center and GPU Accelerated Processing Division, you will drive IP domain and power-management validation for AMD Data Center GPU products…
Added 4 days ago
ASIC Physical Design Engineer
Movellus Inc.
Toronto, ON · Greater Toronto Area, Canada
Full-time
We’re seeking a motivated and skilled ASIC Physical Design Engineer to join our growing engineering team. This role offers an exciting opportunity to contribute to the physical realization…
Added 5 days ago
RTL Design Engineer
Advanced Micro Devices, Inc
Markham, ON
Full-time
As a RTL Design Engineer on the T&E NBIO/PCIe Subsystem team, you will help bring cutting-edge silicon designs to life. You will contribute to RTL and IP logic design while collaborating…
Added 6 days ago
Senior ASIC RTL Design Engineer
USA Tech Recruit
Ottawa, ON
$150,000 to $200,000 CAD / year
Full-time
We are looking for a Senior ASIC RTL Design Engineer to join a long-term client engagement focused on an advanced I/O chiplet combining die-to-die connectivity with multi-protocol,…
Added 7 days ago
SOC Design Engineer
Qualcomm
Vancouver, BC · Markham, ON · Toronto, ON
Full-time
…create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP…
Added 6 days ago
Physical Design Engineer
Mirafra Technologies
ON · Ontario, Canada
Full-time
We are seeking a Physical Design Engineer with a strong foundation in Static Timing Analysis (STA) and a focus on design flow automation. In this role, you will be responsible for driving…
Added 6 days ago
Verification Engineer V
TekWissen ®
Markham, ON
$104.57 USD / hour
Contract
Join Display IP team at AMD that is building industry-leading semiconductor products and technologies. As a Verification Engineer 5, you will play a key role in defining, developing, and…
Added 7 days ago
Senior ASIC Verification Engineer – SystemVerilog / UVM / High-Speed I/O / SoC / Chipsets
USA Tech Recruit
Ottawa, ON
Full-time
Senior ASIC Verification Engineer / Senior Verification Engineer / Staff Verification Engineer / ASIC Verification / SoC Verification / RTL Verification / Hardware Verification /…
Added 7 days ago
Design Verification Engineer
Net2Source (N2S)
Markham, ON
$92 to $102 CAD / hour
Contract
Join Display IP team that is building industry-leading semiconductor products and technologies. As a Verification Engineer 5, you will play a key role in defining, developing, and executing…
Added 21 days ago
Staff PCIe Design Engineer
Arm
Toronto, ON
Full-time
Are you ready for a new and exciting challenge at Arm Toronto's Design Center? If you are a self-motivated design engineer with expertise in micro-architecture, logic design and ARM IP’s,…
Added 14 days ago
Digital - ASIC Design Automation Engineer
Eliyan Corporation
Toronto, ON · Greater Toronto Area, Canada
Full-time
Own the Jenkins-based CI for RTL quality across active design programs: lint, CDC, RDC, elaboration, synthesis, and STA. Optimize for turnaround time, not only coverage.
Added 18 days ago
CAD-DFT Engineer
Arm
Toronto, ON
Full-time
…within Arm's Solutions Engineering organization! As a CAD-DFT Engineer, you will develop and apply scalable strategies, sequences, and automation to optimize Arm-based SoC implementation.…
Added 20 days ago
IOMMU Verification Engineer
AMD
Vancouver, BC
$105,600 to $158,400 USD / year
Full-time
The AMD IOHUB Team (part of the NBIO organization) is looking for an ASIC Design Verification Engineer to join our growing team. We develop leading-edge I/O connectivity and virtualization…
Added 1 month ago
ASIC Design Verification Engineer
AMD
Ottawa, ON · Kanata, ON
$105,600 to $158,400 USD / year
Full-time
Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues
Added 20 days ago
Firmware Engineer – SerDes PHY (all levels)
Qualcomm
Toronto, ON
Full-time
We are looking for an experienced Firmware Engineer to lead firmware architecture, development, integration, and bring-up for our SerDes PHY portfolio. The ideal candidate has driven…
Added 20 days ago
Senior SoC Design Engineer
Microchip Technology Inc.
Burnaby, BC · Canada - Burnaby
Full-time
As a Senior Engineer I-Design , your job will be contributing to the following areas under guidance of experienced leaders in product development field:
Added 20 days ago
Design Verification Engineer
Advanced Micro Devices, Inc
Vancouver, BC
Full-time
AMD is seeking an experienced Design Verification Engineer to join our team developing next-generation high-performance computing and semiconductor products. In this role, you will be…
Added 21 days ago
Principal Engineer, CAD
SiTime Corporation
Ottawa, ON
Full-time
The Principal Engineer, CAD will provide CAD Software support for Digital, Analog and Mixed-Signal designs, using Cadence, Synopsys, Siemens, Keysight & 3rd party vendor tools.…

USA Tech Recruit

Senior ASIC RTL Design Engineer

Ottawa, ON, Canada

Pay: $150,000 to $200,000 CAD / year
Job type: Full-time
Apply by: Oct 16, 2026
Experience: 10+ years of hands-on ASIC RTL design experience, including ownership of designs through successful tape-out.
Posting language: English
Posted: Sep 16, 2026

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Original job description

A specialist engineering consultancy supporting advanced ASIC, FPGA, and embedded systems development is partnering with a global technology company developing high-performance silicon for next-generation connectivity and networking applications.

We are looking for a Senior ASIC RTL Design Engineer to join a long-term client engagement focused on an advanced I/O chiplet combining die-to-die connectivity with multi-protocol, high-speed I/O. The technology brings together interfaces including UCIe, PCIe, Ethernet, static switching, and an embedded management subsystem.

You will work closely with architecture, RTL, verification, firmware, physical design, and IP teams, taking ownership of assigned design blocks from architectural specification through front-end sign-off. The role combines custom datapath and control logic with the integration of third-party protocol and PHY IP, with a strong emphasis on power, performance, area, and physical implementation.

Client identity and detailed programme specifications will be shared confidentially during the interview process.

Key Responsibilities:

Define block-level microarchitecture, interface specifications, latency, throughput, and resource budgets.
Translate architectural requirements into clean, synthesizable SystemVerilog and Verilog RTL.
Develop configurable static-switch fabrics, protocol multiplexers, pipelined datapaths, and boundary rate-adaptation logic.
Configure and integrate complex protocol and PHY IP, including clocking, reset, status, and control interfaces.
Implement CSR access, configuration sequencing, interrupts, and management logic in collaboration with firmware teams.
Develop assertions and resolve lint, CDC, RDC, and connectivity findings.
Develop timing constraints, analyze synthesis results, and work closely with physical design teams on partitioning, congestion, and timing closure.
Implement low-power controls and support power-intent checks, DFT integration, and formal equivalence activities.
Debug design issues in partnership with verification engineers and maintain clear, accurate technical documentation.
Lead design reviews and communicate technical risks, challenges, dependencies, and progress clearly.
Deliver reviewed RTL and synthesis handoffs aligned with project milestones and front-end sign-off requirements.

Key Qualifications:

10+ years of hands-on ASIC RTL design experience, including ownership of designs through successful tape-out.
Strong expertise in SystemVerilog and Verilog, with a track record of translating specifications into maintainable, production-quality RTL.
Strong experience with high-bandwidth datapaths, pipelining, multiplexing, and multi-clock designs.
Practical experience integrating complex IP and at least one high-speed interface such as PCIe, Ethernet, or die-to-die interconnect.
Strong understanding of CDC, RDC, reset sequencing, assertions, and static design checks.
Hands-on experience with synthesis, timing constraints, and timing-report analysis.
Experience working closely with physical design teams to resolve timing, congestion, and implementation challenges.
Scripting experience with Python, Tcl, or similar languages for design-flow automation.
Ability to take ownership of significant technical decisions, lead design reviews, and drive blocks through front-end sign-off.
Strong communication skills and the ability to work effectively across architecture, verification, firmware, physical design, and IP teams.

Nice to Have:

Experience with UCIe or other chiplet interconnect technologies, including protocol-to-PHY integration and advanced packaging considerations.
Experience with PCIe Gen6/Gen7, 200G Ethernet, or 224G PAM4 SerDes integration.
Experience delivering advanced-node ASICs.
Experience implementing low-power designs using UPF.
Experience developing physically aware RTL partitions.
Experience with embedded RISC-V subsystems, AXI/APB, secure boot, sideband management, or FPGA prototyping.

By applying to this role you understand that we may collect your personal data and store and process it on our systems. For more information please see our Privacy Notice https://eu-recruit.com/wp-content/uploads/2024/07/European-Tech-Recruit-Privacy-Notice-2024.pdf

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More about this job

Responsibilities

You will define block-level microarchitecture and translate requirements into synthesizable SystemVerilog and Verilog RTL. The role involves integrating complex protocol and PHY IP while collaborating with cross-functional teams to ensure successful front-end sign-off.

Requirements

Candidates must have 10+ years of hands-on ASIC RTL design experience with a proven track record of successful tape-outs. Strong expertise in high-bandwidth datapath design, timing constraints, and industry-standard verification and implementation flows is required.

Skills

ASIC RTL Design
SystemVerilog
Verilog
PCIe
Ethernet
UCIe
High-speed I/O
Synthesis
Timing Closure
CDC
RDC
Python
Tcl
Low-power design
UPF
DFT

Visa sponsorship

Not detected in the job text

Keywords

ASIC
RTL Design
SystemVerilog
Verilog
PCIe
Ethernet
UCIe
Chiplet
Synthesis
Timing Closure
CDC
RDC
Python
Tcl
Low-power
UPF
DFT
Datapath
PHY IP
Microarchitecture
Semiconductor
Networking
Connectivity
Front-end sign-off
Tape-out
Static-switch fabrics
CSR
Firmware
Physical design
Embedded systems

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