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Added 1 month ago
F
Search Engineer
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- Full-time
…fingerprinting that evolve weekly. This role is equal parts research and engineering: understand how those systems work at the deepest level, then turn that understanding into…
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- Full-time
The Data Engineer will be responsible for building and maintaining the data integration infrastructure that underpins Trafigura's North American Gas and Power trading desk. Working within…
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Added 1 month ago
UT
Senior ASIC Verification Engineer – SystemVerilog / UVM / High-Speed I/O / SoC / Chipsets
USA Tech Recruit
Ottawa, ON
- Full-time
Verify static switching configurations, protocol modes, data integrity, latency, throughput, reset behaviour, and recovery mechanisms
Added 1 month ago
Analytics Intern (Fall 2026 Term) - Engineering
Orennia
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Orennia provides an all-in-one platform for accurate data, predictive analytics and actionable insights across the energy transition. We drive faster capital allocation decisions and help…
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Senior Full Stack Software engineer
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- Full-time
On behalf of our client, Affinity is seeking an experienced Senior Full Stack Developer to join their engineering team in Canada. This is a full-time opportunity for a seasoned engineer who…
Added 1 month ago
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Senior Fuel Engineering Analyst
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…preferably in a cloud environment (e.g., BigQuery). Familiarity with Python for data analysis is a strong…
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…translating insights into practical value levers, and using data, digital tools and artificial intelligence to move from diagnostic to decision and execution. You will work with private…
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Ecolab Inc.
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Montreal, QC
- Full-time
You will report to the Director of Engineering.
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Qualcomm
Markham, ON
- Full-time
Interns Group, Interns Group > Interim Engineering Intern - HW
Added 1 month ago
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FY27 Intern - Low-Power AI, Audio, and Sensors Subsystem Engineering Internship - ASIC Firmware / Embedded - Canada (12 or 16 months)
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Interns Group, Interns Group > Interim Engineering Intern - HW
Added 1 month ago
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We are looking for an IT Network Specialist to join a global network engineering team responsible for designing, operating, and continuously improving a mission-critical enterprise network…
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Added 1 month ago
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Data Engineering Manager, Regulatory Compliance
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TeamBuilders Consulting is seeking an experienced Software Developer – Industrial Data & Automation for their client, a growing technology and engineering organization.
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Software Developer - C++ (Co-op)
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- $3,600 to $4,500 CAD / month
Apera AI is seeking a Software Developer (Co-op) with strong C++ skills and an interest in robotics to join our Apera Vue engineering team for the 8 months term period (Jan 2027 - August…
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Machine Learning Applied Scientist (Co-op)
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USA Tech Recruit

Senior ASIC Verification Engineer – SystemVerilog / UVM / High-Speed I/O / SoC / Chipsets

Ottawa, ON, Canada

Full-time

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Job details

Job type: Full-time
Experience: 10+ years of hands-on ASIC design verification experience
Posting language: English
Posted: Sep 16, 2026

Original job description

Senior ASIC Verification Engineer – SystemVerilog / UVM / High-Speed I/O / SoC / Chipsets

We are currently partnered with a semiconductor technology organisation developing advanced I/O and chipset solutions that connect die-to-die interfaces with high-speed, multi-protocol I/O. The technology combines advanced interconnect standards, high-speed networking, switching, and embedded management capabilities.

As part of their continued development of complex silicon solutions, they are looking to hire a Senior ASIC Verification Engineer to establish and execute verification strategies across blocks, subsystems, and chip-level functions. The role involves close collaboration with architecture, RTL, verification, firmware, physical design, and IP teams, with ownership extending through verification closure and tape-out.

Key responsibilities

Develop verification plans that map requirements to test scenarios, verification platforms, coverage goals, and sign-off criteria
Translate architectural and design requirements into measurable verification objectives
Design and maintain reusable SystemVerilog/UVM verification environments, including sequences, agents, scoreboards, reference models, and assertions
Integrate third-party verification IP (VIP) and models
Verify configured IP and end-to-end connectivity across protocol and PHY interfaces
Verify static switching configurations, protocol modes, data integrity, latency, throughput, reset behaviour, and recovery mechanisms

Key requirements

10+ years of hands-on ASIC design verification experience
Proven ownership of verification activities through tape-out and formal sign-off
Expert-level SystemVerilog and UVM experience
Strong understanding of constrained-random verification and reusable testbench architecture
Proven experience developing verification plans, defining coverage objectives, debugging complex failures, and driving verification closure
Experience verifying high-speed interfaces, complex SoCs, networking ASICs, or die-to-die interconnect technologies
Hands-on experience integrating verification IP and developing reference models and scoreboards

Keywords

Senior ASIC Verification Engineer / Senior Verification Engineer / Staff Verification Engineer / ASIC Verification / SoC Verification / RTL Verification / Hardware Verification / Semiconductor Verification / Design Verification / SystemVerilog / UVM / Universal Verification Methodology / Constrained-Random Verification / Coverage-Driven Verification / Assertion-Based Verification / SystemVerilog Assertions / SVA / Verification Planning / Verification Closure / Verification Sign-Off / ASIC / SoC / Chipset / Chipset Verification / Die-to-Die / D2D / I/O Verification / High-Speed I/O / High-Speed Interfaces / Networking ASIC / Networking Silicon / UCIe / PCIe / PCIe Gen6 / PCIe Gen7 / Ethernet / Ethernet PCS / Ethernet FEC / SerDes / 224G SerDes / PHY Verification / Protocol Verification / Protocol VIP / Verification IP / VIP Integration / Reference Models / Scoreboards / Testbenches / Verification Environments / Sequences / Agents / Functional Coverage / Code Coverage / Assertion Coverage / Regression Automation / Python / Perl / Scripting / Failure Triage / Debugging / CDC / Clock Domain Crossing / RDC / Reset Domain Crossing / Formal Verification / Formal Model Checking / Connectivity Verification

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More about this job

Responsibilities

Establish and execute verification strategies across blocks, subsystems, and chip-level functions for advanced I/O and chipset solutions. Develop verification plans and maintain reusable SystemVerilog/UVM environments to ensure verification closure and successful tape-out.

Requirements

Requires over 10 years of hands-on ASIC design verification experience with expert-level proficiency in SystemVerilog and UVM. Candidates must have a proven track record of driving verification closure for high-speed interfaces or complex SoCs through tape-out.

Skills

SystemVerilog
UVM
ASIC Verification
High-Speed I/O
SoC Verification
Constrained-Random Verification
Verification Planning
Verification IP (VIP)
Reference Models
Scoreboards
Assertion-Based Verification
Functional Coverage
Die-to-Die Interconnect
Networking ASICs
Python
Perl

Visa sponsorship

Not detected in the job text

Keywords

ASIC
SoC
Chipset
SystemVerilog
UVM
Universal Verification Methodology
Constrained-Random Verification
Coverage-Driven Verification
SVA
Verification Sign-Off
Die-to-Die
D2D
High-Speed I/O
Networking Silicon
UCIe
PCIe Gen6
PCIe Gen7
Ethernet
SerDes
PHY Verification
Protocol VIP
Regression Automation
Python
Perl
CDC
RDC
Formal Verification
Connectivity Verification
Semiconductor

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