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W3Global

Design Verification Engineer with GLS (gate level simulation)

  • Canada

Contract

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Job details

Job type
Contract
Posting language
English
Posted

Original job description

Must: design verification engineers with GLS (Gate level simulation), UVM, PCIe, UCIe, ethernet verification experience

ASIC Programs (Switch/NIC) DV

  • Lead or contribute to verification of 4-5 ASIC design blocks.
  • Develop UVM-based verification environments, sequences, tests, debug, and coverage closure.
  • Strong experience in SystemVerilog/UVM and GLS
  • Experience with PCIe, UCIe 2.0, and Ethernet protocols.
  • Ability to independently own verification deliverables.
  • Support customer collaboration in EST timezone.

Required Skills

  • Strong SystemVerilog/UVM verification experience
  • Knowledge and/or hands-on experience with:
  • UCIe 2.0
  • PCIe
  • Ethernet
  • Ability to own design blocks independently and drive verification closure

Responsibilities

The DV team is expected to:

  • Own verification of 4-5 design blocks per ASIC
  • Develop and execute sequences
  • Perform test development and debug
  • Drive coverage collection and closure
  • Own end-to-end verification execution for assigned blocks
  • The customer will own the testbench infrastructure.

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More about this job

Responsibilities

Own verification for four to five ASIC design blocks, developing and executing UVM sequences and tests, debugging issues, and driving coverage collection and closure. Independently manage end-to-end verification deliverables and support customer collaboration in the EST time zone.

Requirements

Requires strong SystemVerilog/UVM and gate-level simulation experience, with knowledge or hands-on experience in PCIe, UCIe 2.0, and Ethernet. Candidates must be able to independently own design blocks and drive verification to closure.

Skills

  • SystemVerilog
  • UVM
  • Gate-Level Simulation
  • Design Verification
  • PCIe
  • UCIe 2.0
  • Ethernet
  • ASIC Verification
  • Test Development
  • Debugging
  • Coverage Closure
  • Verification Ownership
  • Customer Collaboration

Visa sponsorship

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Categories

  • Engineering
  • Technology
  • Software
  • Management & Leadership

Keywords

  • Design Verification
  • Gate-Level Simulation
  • GLS
  • SystemVerilog
  • UVM
  • PCIe
  • UCIe 2.0
  • Ethernet
  • ASIC
  • ASIC Programs
  • Switch
  • NIC
  • Verification Environment
  • Sequences
  • Test Development
  • Debugging
  • Coverage Collection
  • Coverage Closure
  • Verification Execution
  • Design Blocks
  • Customer Collaboration
  • EST Time Zone

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