Closed listing
Design Verification Engineer with UVM
- Canada
Contract
This opening has closed.
The original listing is kept below for reference.
Job details
- Job type
- Contract
- Posting language
- English
- Posted
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Search current openingsOriginal job description
Archived listing. The details below describe a past opening.
Must: design verification engineers with UVM, PCIe, UCIe, ethernet verification experience
ASIC Programs (Switch/NIC) DV
The DV team is expected to:
ASIC Programs (Switch/NIC) DV
- Lead or contribute to verification of 4-5 ASIC design blocks.
- Develop UVM-based verification environments, sequences, tests, debug, and coverage closure.
- Strong experience in SystemVerilog/UVM.
- Experience with PCIe, UCIe 2.0, and Ethernet protocols.
- Ability to independently own verification deliverables.
- Support customer collaboration in EST timezone.
- Strong SystemVerilog/UVM verification experience
- Knowledge and/or hands-on experience with:
- UCIe 2.0
- PCIe
- Ethernet
- Ability to own design blocks independently and drive verification closure
The DV team is expected to:
- Own verification of 4-5 design blocks per ASIC
- Develop and execute sequences
- Perform test development and debug
- Drive coverage collection and closure
- Own end-to-end verification execution for assigned blocks
- The customer will own the testbench infrastructure.
More about this job
Responsibilities
Own or contribute to verification for four to five ASIC design blocks, developing and executing UVM-based sequences and tests. Debug issues, drive coverage collection and closure, and manage end-to-end verification for assigned blocks while collaborating with the customer in the EST time zone.
Requirements
Requires strong SystemVerilog and UVM verification experience, along with knowledge or hands-on experience in UCIe 2.0, PCIe, and Ethernet. Candidates must be able to independently own design blocks and drive verification to closure.
Skills
- SystemVerilog
- UVM
- ASIC Verification
- PCIe
- UCIe 2.0
- Ethernet
- Verification Environment Development
- Sequence Development
- Test Development
- Debugging
- Coverage Closure
- Design Block Ownership
- End-to-End Verification
Visa sponsorship
Not detected in the job text
Categories
- Engineering
- Technology
- Software
- Management & Leadership
Keywords
- SystemVerilog
- UVM
- ASIC
- Design Verification
- PCIe
- UCIe 2.0
- Ethernet
- Switch
- NIC
- Verification Environment
- Sequences
- Test Development
- Debugging
- Coverage Collection
- Coverage Closure
- Design Blocks
- End-to-End Verification
- Customer Collaboration
- EST Time Zone