RTL Design Engineer – PCIe
- Canada
Contract
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Job details
- Job type
- Contract
- Posting language
- English
- Posted
Original job description
Key Responsibilities & Required Skills
- Strong hands-on experience in RTL Design using Verilog/SystemVerilog.
- Hands-on experience in verification of PCIe Gen3/Gen4/Gen5 protocols.
- Good understanding of digital design fundamentals, including FSM design, pipelining, CDC, reset architecture, synchronizers and low-power design concepts.
- Experience in micro-architecture development and RTL implementation.
- Knowledge of synthesis constraints and timing concepts.
- Familiarity with Lint, CDC, STA and low-power verification methodologies.
- Strong debugging and problem-solving skills.
Preferred Qualifications
- Bachelor's or Master's degree in ECE, EEE, Electronics or a related engineering discipline.
- Relevant experience in RTL Design and/or PCIe Design Verification.
- Good understanding of ASIC design and verification flows.
More about this job
Responsibilities
Develop microarchitecture and implement RTL using Verilog or SystemVerilog. Verify PCIe Gen3, Gen4, and Gen5 protocols, and apply digital design, timing, and low-power methodologies.
Requirements
The role requires hands-on RTL design experience and experience verifying PCIe protocols, along with knowledge of digital design fundamentals and ASIC design flows. A bachelor's or master's degree in ECE, EEE, Electronics, or a related engineering discipline is preferred.
Skills
- RTL Design
- Verilog
- SystemVerilog
- PCIe Protocol Verification
- Digital Design
- Finite State Machine Design
- Pipelining
- Clock Domain Crossing
- Reset Architecture
- Synchronizers
- Low-Power Design
- Microarchitecture Development
- RTL Implementation
- Synthesis Constraints
- Static Timing Analysis
- Lint
Visa sponsorship
Not detected in the job text
Categories
- Engineering
- Technology
- Software
Keywords
- RTL Design
- Verilog
- SystemVerilog
- PCIe
- PCIe Gen3
- PCIe Gen4
- PCIe Gen5
- Digital Design
- Finite State Machines
- Pipelining
- Clock Domain Crossing
- Reset Architecture
- Synchronizers
- Low-Power Design
- Microarchitecture
- RTL Implementation
- Synthesis Constraints
- Timing Concepts
- Lint
- Static Timing Analysis
- Low-Power Verification
- ASIC Design
- Design Verification
- Debugging