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UVM Verification Engineer

  • Canada

Contract

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Job details

Job type
Contract
Posting language
English
Posted

Original job description

Strong experience in Design Verification using SV and UVM.

· Hands-on experience in verification of PCIe (Gen3/Gen4/Gen5) protocols.

· Good understanding of PCIe architecture, LTSSM, transaction layer, data link layer, and physical layer concepts.

· Exposure to protocols such as AXI, APB, AHB

· Experience in developing reusable verification components and environments.

· Knowledge of assertions (SVA), coverage-driven verification, and constrained-random methodologies.

· Experience with industry-standard simulators such as VCS, Xcelium, or Questa.

· Strong debugging and problem-solving skills.

More about this job

Responsibilities

Develop and use SystemVerilog and UVM verification environments, including reusable components, to verify PCIe protocols across Gen3, Gen4, and Gen5. Apply assertions, coverage-driven verification, and constrained-random methodologies, and debug issues using industry-standard simulators.

Requirements

Requires strong design verification experience with SystemVerilog and UVM, plus hands-on PCIe protocol verification experience. Candidates should understand PCIe architecture and layers, have exposure to AXI, APB, or AHB, and be familiar with VCS, Xcelium, or Questa.

Skills

  • SystemVerilog
  • UVM
  • PCIe Verification
  • PCIe Architecture
  • LTSSM
  • Transaction Layer
  • Data Link Layer
  • Physical Layer
  • AXI
  • APB
  • AHB
  • Reusable Verification Components
  • SystemVerilog Assertions
  • Coverage-Driven Verification
  • Constrained-Random Verification
  • Debugging

Visa sponsorship

Not detected in the job text

Categories

  • Engineering
  • Technology
  • Software

Keywords

  • SystemVerilog
  • UVM
  • Design Verification
  • PCIe
  • PCIe Gen3
  • PCIe Gen4
  • PCIe Gen5
  • PCIe Architecture
  • LTSSM
  • Transaction Layer
  • Data Link Layer
  • Physical Layer
  • AXI
  • APB
  • AHB
  • Reusable Verification Components
  • Verification Environments
  • SVA
  • Coverage-Driven Verification
  • Constrained-Random Methodologies
  • VCS
  • Xcelium
  • Questa
  • Debugging
  • Problem-Solving

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