Closed listing
Design Verification Engineer
- Toronto, ON, Canada
Full-time
This opening has closed.
The original listing is kept below for reference.
Job details
- Job type
- Full-time
- Closing date
- Experience
- 3+ years of experience in Design Verification, ASIC Verification, or SoC Verification.
- Posting language
- English
- Posted
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Search current openingsOriginal job description
Archived listing. The details below describe a past opening.
Required Qualifications
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- 3+ years of experience in Design Verification, ASIC Verification, or SoC Verification.
- Strong knowledge of digital design fundamentals and computer architecture.
- Hands-on experience with SystemVerilog, UVM, and assertion-based verification (SVA).
- Experience with verification tools such as Synopsys VCS, Cadence Xcelium, or Siemens QuestaSim.
- Knowledge of scripting languages such as Python, Perl, or Shell.
- Experience with debugging RTL designs and simulation environments.
- Understanding of industry-standard protocols such as AXI, PCIe, USB, Ethernet, I2C, SPI, or DDR.
Preferred Qualifications
- Experience with SoC integration and subsystem verification.
- Knowledge of formal verification methodologies.
- Exposure to FPGA prototyping and emulation platforms.
- Experience with C/C++ programming and embedded systems.
- Familiarity with low-power verification techniques (UPF/CPF).
Required Skills
- SystemVerilog
- UVM Methodology
- ASIC/SoC Verification
- Functional Verification
- RTL Debugging
- Coverage Analysis
- Scripting (Python/Perl/Shell)
- Assertion-Based Verification (SVA)
- Simulation & Regression Management
More about this job
Responsibilities
Perform design verification for ASIC and SoC designs, including functional verification, RTL debugging, and coverage analysis. Use SystemVerilog, UVM, assertions, simulation tools, and scripting to manage verification and regression activities.
Requirements
Requires a bachelor's or master's degree in Electrical Engineering, Computer Engineering, or a related field, plus at least three years of design, ASIC, or SoC verification experience. Candidates should have hands-on SystemVerilog, UVM, SVA, simulation-tool, scripting, RTL-debugging, and industry-standard protocol experience; SoC integration, formal verification, FPGA emulation, C/C++, embedded systems, and low-power verification are preferred.
Skills
- SystemVerilog
- UVM Methodology
- ASIC/SoC Verification
- Functional Verification
- RTL Debugging
- Coverage Analysis
- Python
- Perl
- Shell Scripting
- Assertion-Based Verification
- Simulation and Regression Management
- Digital Design
- Computer Architecture
- Industry-Standard Protocols
- Formal Verification
- Low-Power Verification
Visa sponsorship
Not detected in the job text
Categories
- Engineering
- Technology
- Software
Keywords
- Design Verification
- ASIC Verification
- SoC Verification
- SystemVerilog
- UVM
- Assertion-Based Verification
- SVA
- Synopsys VCS
- Cadence Xcelium
- Siemens QuestaSim
- Python
- Perl
- Shell
- RTL Debugging
- AXI
- PCIe
- USB
- Ethernet
- I2C
- SPI
- DDR
- SoC Integration
- Subsystem Verification
- Formal Verification
- FPGA Prototyping
- Emulation Platforms
- C/C++
- Embedded Systems
- UPF
- CPF