Bachelor's degree in Electrical Engineering, Computer Engineering, or a related discipline.
5+ years of experience in ASIC or SoC Physical Design.
Hands-on expertise with Cadence Genus for synthesis and Cadence Innovus for floorplanning and implementation.
Experience working on large, high-performance semiconductor designs with demanding timing requirements.
Strong knowledge of synthesis, timing analysis, physical implementation, and PPA optimization.
Experience with advanced semiconductor process technologies such as 5nm, 3nm, or newer.
Excellent communication skills and the ability to work effectively with RTL, architecture, physical design, and implementation teams.
