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Responsibilities
The role involves developing RTL for compute subsystems, controllers, datapaths, and interfaces, as well as contributing to microarchitecture definition and technical reviews. Additionally, the engineer will build UVM-based verification environments and test plans, drive functional coverage, and support FPGA bring-up and silicon validation activities.
Requirements
Candidates should have a strong background in RTL coding, particularly in SystemVerilog or Verilog, and solid experience with UVM and modern DV methodologies. Knowledge of SoC integration, buses, protocols, and exposure to FPGA and subsystem verification is also required.
