Multiple Openings | Ottawa Preferred | Hybrid Flexibility
We're hiring for a few Senior Engineering positions supporting advanced FPGA, ASIC, and chiplet development programs focused on high-performance computing, AI, networking, and high-speed connectivity applications.
We're looking for engineers with 7+ years of experience in FPGA design, ASIC RTL development, or verification who enjoy solving complex technical challenges and working closely with architecture, firmware, verification, and implementation teams. These opportunities involve technologies such as SystemVerilog, UVM, PCIe, Ethernet, UCIe, SerDes, and other high-speed interfaces.
Current Openings
Senior FPGA Design Engineer
- FPGA design using SystemVerilog from specification through timing closure
- RTL development, CDC analysis, synthesis setup, and timing constraints
- Opportunity to grow into a design lead role
Senior RTL Design Engineer
- Front-end RTL development for advanced chiplet and high-speed connectivity solutions
- SystemVerilog and Verilog development, protocol and PHY IP integration
- CDC/RDC analysis, synthesis, and front-end sign-off activities
- Experience with PCIe, Ethernet, UCIe, or other high-speed interfaces is highly desirable
Senior Verification Engineer
- SystemVerilog and UVM-based verification of complex ASIC and chiplet designs
- Verification planning, VIP integration, coverage closure, and sign-off
- Experience with SoC, high-speed interface, or die-to-die verification is an asset
Desired Experience
- 7+ years of FPGA, ASIC, RTL, or verification experience
- Strong SystemVerilog and/or Verilog expertise
- ASIC, FPGA, or SoC development experience
- High-speed interfaces such as PCIe, Ethernet, SerDes, or UCIe
- CDC/RDC methodologies, synthesis, timing analysis, and timing closure
- Python, Tcl, or similar scripting languages
- ASIC tape-out experience is an asset
Work Arrangement
- Ottawa preferred
- Hybrid arrangements may be available depending on the role and project
- Candidates must be eligible to work in Canada
If your background aligns with FPGA design, RTL development, or verification engineering and you're interested in learning more, we'd be happy to connect.
