Archived listing. The details below describe a past opening.
Title: RTL design Engineer 5
Contract: 6 months Extendable
Location: Markham, ON (Hybrid)
Pay Rate: ($75-$80)/hr T4
JOB DUTIES:
- Responsible for RTL design using Verilog HDL for implementation and debug.
- Read and comprehend System on Chip level architectural specification.
- Write microarchitecture specifications for new and modified functions.
- Responsible for linting and simulation of design.
- Work with synthesis and backend teams for physical implementation.
- RTL Design Engineer to help with some IP work
- Need experience with some AI tools, how to use AI tools to speed up the development
- Basic infrastructure knowledge
EDUCATION:
- Bachelor's or Master's in Computer Engineering.
