We are looking for an engineer to design, implement, and validate a flexible, wideband (greater than 6GHz), high dynamic range (more than 60dB) transceiver RF front end (amplifiers, attenuators, up/downconversion, ADC/DAC) and corresponding clock distribution network (using commercial off the shelf components) to interface with a digital system (FPGA), while effectively communicating the design, progress, challenges, and updates to a broader team.
Mandatory Skills
Experience in all of the following areas:
- High Frequency (>20GHz) RF front end design
- Experience designing analog interfaces to high speed ADCs and DACs (>325MSPS)
- End-to-end experience with design and manufacturing of RF boards (schematic capture, layout, initial bring up)
- Working knowledge of C or C++
Minimum Skills
Experience in at least three of the following areas:
- Transistor based LNA Design (<1.5dB)
- Wideband (DC-6GHz+) RF front end design
- Designing wideband matching networks (>2GHz BW)
- Designing wideband RF networks for RF/LO synthesizers (100MHz-6GHz+)
- Use of network analyzers to determine phase noise issues.
- Characterization and optimization of analog front end design
- Design of phase coherent clock distribution networks supporting >8 end devices
Optional Skills
The following skills are desired but not necessarily required for the position:
- Thermal management and passive cooling
- Familiarity with beam forming techniques
- Familiarity with phased arrays and their RF and analog implementation
- Knowledge of clock distribution and timing with JESD204 standard
- Experience designing low jitter (under 1 picosecond) clock distribution to digital and radio devices
- Experience designing low noise power systems (switching/linear regulators)
- Familiarity with antenna design and selection criteria for wideband or multiband applications
- Experience in development from design to manufacturing
- Experience with open source software
NOTE: This is a contractor position for 6 months with option for +6 month extension.
