Responsibilities
Design FPGA IP architecture and implement complex RTL for 4G/5G Radio Units, including optimizing FPGA resources and achieving timing closure. Develop and execute verification and validation plans, integrate hardware with radio and software teams, and mentor junior engineers.
Requirements
Requires proven FPGA and RTL design experience, knowledge of wireless protocols, signal processing, high-speed interfaces, and 4G/5G Radio and O-RAN architecture. Candidates should be familiar with Quartus, Vivado, MATLAB/Simulink, HDL Coder, UVM, and Git; seven or more years of relevant experience is desirable.
