Original job description
USD 85 to 110 per hour, roughly USD 170,000 to 220,000 annualized at full utilization, ben…SystemVerilogUVM testbench architectureFunctional and code coverage closureSystemVerilog Assertions (SVA)Constrained random verificationVCS, Xcelium, or QuestaUSD 80 to 120 per hour, approximately USD 160,000 to 240,000 annualized at full utilizatio…SystemVerilog or VHDLVivado or QuartusTiming closure and SDC/XDC constraintsClock domain crossing designPCIe, Ethernet, or DDR interfacesOn chip debug (ILA or Signal Tap)USD 75 to 100 per hour, approximately USD 150,000 to 200,000 annualized at full utilizatio…SystemVerilog RTL designMicroarchitecture specificationLint and CDC signoff (SpyGlass or similar)Synthesis and static timing (Design Compiler or Genus)AMBA AXI, AHB, or APB integrationLow power design intent (UPF)Own the link, not just the RTL - this role targets engineers who have taken high-speed int…SystemVerilogPCIe/CXLAXI/AMBACDCDDR4Timing closureShip inference datapaths - this role targets engineers who understand the workload, not ju…SystemVerilogRTL DesignFixed-pointAMBA AXISynthesisTiming closureOwn testbench architecture end to end - this role targets engineers who build verification…UVMSystemVerilogSVAAMBA/AXICoverage ClosurePython/TCL
More about this job
Responsibilities
Design and implement FPGA and RTL solutions, taking designs from microarchitecture and RTL through synthesis, timing closure, and signoff. Own verification activities, including testbench architecture, constrained-random testing, assertions, and coverage closure.
Requirements
The role calls for senior-level experience with SystemVerilog or VHDL, FPGA tools such as Vivado or Quartus, and timing constraints and closure. Relevant expertise includes CDC, high-speed interfaces such as PCIe, Ethernet, or DDR, verification methodologies and tools, synthesis, and static timing analysis.
Skills
- SystemVerilog
- RTL Design
- FPGA Design
- Timing Closure
- UVM
- Functional and Code Coverage
- SystemVerilog Assertions
- Constrained-Random Verification
- Vivado
- Quartus
- Clock Domain Crossing
- PCIe
- Ethernet
- DDR
- AMBA AXI
- Static Timing Analysis
Visa sponsorship
Not detected in the job text
Categories
- Engineering
- Technology
- Manufacturing
Keywords
- SystemVerilog
- VHDL
- RTL Design
- FPGA
- UVM
- Testbench Architecture
- Functional Coverage
- Code Coverage
- SystemVerilog Assertions
- Constrained-Random Verification
- VCS
- Xcelium
- Questa
- Vivado
- Quartus
- Timing Closure
- SDC Constraints
- XDC Constraints
- Clock Domain Crossing
- PCIe
- CXL
- Ethernet
- DDR4
- On-Chip Debug
- ILA
- Signal Tap
- SpyGlass
- Design Compiler
- Genus
- AMBA AXI
