Senior Custom IC Layout Engineer – Memory, Analog/RF & FinFET
Location: Vancouver, Canada_ Hybrid
Experience: 5+ Years
Domain: Semiconductor / VLSI / Chip Design
Job Description:
5+ years of experience in Custom IC Layout / Memory / Analog-RF Layout.
Strong hands-on experience with FinFET technologies; 3nm/5nm exposure mandatory.
Experience in Memory Leafcell layout, memory architectures, and top-level integration.
Develop transistor-level layouts for Bandgap, LDO, ADC/DAC, PLL, LNA, Mixers, PA, Filters, and Modulators.
Strong expertise in Cadence Virtuoso / Virtuoso XL and Calibre.
Proficient in DRC, LVS, ERC, DFM, extraction, and physical verification.
Strong knowledge of device matching, parasitic reduction, RF shielding, high-frequency routing, EM, RC delay, and signal coupling.
Knowledge of Guard Rings, DNW, PN Junctions, LOD, WPE, and advanced process effects.
Experience with RF Transceiver Layout and Deep Sub-Micron CMOS.
Strong collaboration skills with Circuit Design, Memory, and RF/Analog teams.
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